The present invention is generally directed to the testing of complex logic circuits using randomly generated signal patterns. More particularly, the present invention is directed to a method for distributing the output signal lines from a shift register latch string amongst the inputs to a logic circuit so as to improve test coverage and flexibility. Even more particularly, the invention is directed to level sensitive scan design (LSSD) methodologies for test circuit design.
As integrated circuit chip devices have become more densely packed with electronic components and more complex, the need for testing such circuits has grown significantly. This is especially true of digital logic circuits. In order to provide a mechanism for testing complex circuitry of this type, a number of built-in self test (BIST) methodologies have been employed including level sensitive scan design techniques. In the LSSD methodology, a long string of shift register latches is employed in a dual function role which does not detract from normal circuit operation. In particular, the shift register latch string provides both normal input during circuit operation and also provides a mechanism for providing test input signals to the circuit for diagnostic purposes. These tests may be employed immediately subsequent to chip manufacture or may in fact be employed in the field to diagnose error conditions. Depending on the source of input signals to the shift register latch scan string, either normal operations or test operations may be carried out.
Because of the usually large number of input signal lines and the combinatorially large number of possible inputs to these signal lines, random test pattern generation is generally employed to insure complete and uniform coverage of all important test conditions that could arise. The present invention is particularly directed to so-called AC or delay testing of the logic circuit. In this particular form of test, it is important to provide two distinct sets of signal values to the logic circuit at closely spaced time intervals so as to best ascertain whether or not a fault condition exists. With current approaches to this problem, where one test pattern follows closely after another, the test pairs are very highly correlated and thus are limited in the number of different pairs of test patterns which can be applied.
One of the concepts that is important to grasp for an understanding of the present invention, is the notion of a "cone of logic". In any given logic circuit, there are input and output signal lines. Not every input line can generally influence every output signal line. Conversely, each output signal line is generally influencable only by a subset of input signal lines. Thus, each output signal line is associated with a cone of logic representing signal paths through which input signals influence the output signal. Furthermore, it is seen that an input signal line can in fact influence the output at more than one output signal line. Thus, one can associate with each output signal line a subset of input signal lines passing through and defining the cone of logic. Concomitantly, one can associate with each input signal line a subset of output signal lines which can be influenced by the input signal present on any selected input signal line.